XGUDP – 10G & 25Gbit/s Ethernet UDP/IP Offload Engine for FPGAs

User Datagram Protocol (UDP/IP) is a communications protocol used for establishing connections between applications on the Internet. The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where low latency is a priority and some data loss is acceptable, such as video and audio streaming. Chevin Technology’s 10G & 25G UDP Ethernet IP core for FPGAs  has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality.

Chevin Technology’s 10G &25G UDP Ethernet IP core is configurable for Xilinx FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technology’s UDP IP core is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals.
A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by a single UDP IP core by using the TDEST sideband embedded in the streaming interface.

Throughput & Latency Figures:

UDP send/receive rate: 10GBPS (1.25GB/s), TX 38.4 ns, RX 38.4 ns

Round trip delay MAC -> APP -> MAC 102.4ns (Figures include 33.6ns of inherent protocol latency)

FPGA Resource Figures: Virtex UltraScale: 2480 LUTs; Kintex Ultrascale: 2480 LUTs; Kintex-7: 3088 LUTs

Small Memory Footprint 14 RAMS

Options:+ ARP/ICMP 920 LUTS

Key Features

  • AXI4s MAC & Application Interfaces
  • Designed to UDP specification RFC768
  • Compose/Decompose complete UDP Datagrams
  • IP frame Checksum Generator/Checker
  • Jumbo frame support up to 32k
  • Configurable operation port filtering
  • 1-64k Ports (configurable ports & filters)
  • Detailed traffic analysis statistics collection
  • Integrated Streaming FIFO – 4 Block RAMs
  • Flow Control between MAC/User logic
  • Consistently low and predictable latency with zero frame jitter

Lower Layer IP Blocks

  • CT1009-XGMAC 10Gbit/s Ethernet MAC for low-latency/high performance FPGA applications
  • CT1006-XGARP/ICMP 10Gbit/s Ethernet layers for complete FPGA hosted application with ARP and ICMP “ping”
  • CT1010-XGPCS 10Gbit/s Ethernet PCS for ultra low-latency 64b66b coding & SERDES to 10.3125Gbit line rate

Contact us for datasheet and pricing

Chevin Technology XGUDP 10GBIT diagram 2