XGMAC – 10Gbit/s Ethernet MAC IP for FPGAs

The CT1009-XGMAC IP core is an Ultra Low-Latency 10Gbit/s Ethernet MAC with a latency of 44.8ns in 2749 LUTs.

When combined with the Ultra Low-Latency XGPCS, the full packet round trip time ( MAC Input -> Wire -> MAC Output ) is 153.8ns in 5153 LUTs.

The XGMAC complies with the IEEE802.3-2008 specification, and provides an easy path to the integration of protocols such as TCP/IP and UDP protocols in an FPGA, whilst using minimal FPGA resources. The XGMAC simplifies the synthesis of ultra fast Duplex 10Gbit/s Ethernet for FPGAs.

We understand that efficiency is crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 156.25MHz.

Latency of the XGMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 19 nanoseconds after arriving at XGMII. Alternatively, the Store-and-Forward mode reduces application workload, as the XGMAC drops all corrupt frames. The Frame Checksum verifies frame integrity; the CRC32 check result is available 32 nanoseconds after the final byte is received.

The Deficit Idle Count optimizes the Inter Frame Gap (IFG) for absolute maximum Throughput and minimum Latency by maintaining an average IFG count.

10G Ethernet IP Cores
PRODUCTFull Packet Round Trip TimeLUTS
XG LL MAC/ PCS153.8ns5153
XG UDPFrame Length + 82ns1348
XG TCPFrame Length + 176ns2-5k

Key Features

  • 10Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3-2008 specification
  • Low latency, TX 32ns, RX 19ns (Modes: cut-through/store-and-forward)
  • Integrated FCS(CRC32) checker and generator
  • Small Footprint, Kintex UltraScale 2749 LUTs / 2 Block RAMs
  • Pause packet generate/accept
  • Deficit Idle Control / Programmable IFG, less gaps, more throughput
  • Store-and-forward /Cut-Through FIFO modes for minimum workload/latency
  • Statistics counters, TX and RX traffic stats collected in size bins, frame type, FCS errors
  • Local/Remote fault handling at RS Sub-Layer
  • MAC Filter/Promiscuous Mode
  • Easy to integrate, simple host interface to registers and statistics table.


  • Xilinx AXI4 streaming interface
  • VLAN 802.1Q & PFC priority flow control
  • IEEE 1588 Precision Time Protocol
  • Advanced Hash Table based Filters, MAC address, IP, TCP/UDP port
  • Encrypted Netlist

Lower Layer IP Blocks Network Side

  • Connect to SFP+ (copper Direct Attach or optical Fibre) with Chevin Technology XGPCS (PCS-PMA,10GBASE-R)
  • Connect to back-plane or PHY chip with Xilinx XAUI IP

Upper Layers IP Blocks Application Side

Contact us for datasheet and pricing