TCP/IP – 10 & 25Gbit/s TCP Offload Engine for FPGAs

The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks. The TCP/ IP stack can be used with Chevin Technology’s 10G & 25G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources.

Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol using fast and efficient logic for checksum calculation. Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto FPGA logic. Using the FPGA to analyse packets instead of the CPU significantly increases data transfer time and consistently reduces jitter.

The TCP/IP is easily integrated alongside other protocols to provide an easy path for the development of TCP enabled FPGA applications.

Chevin Technology offer flexible licensing terms and engineering support packages to suit the requirements of each customer.

Contact us today to discuss your project goals.

 

Key Features

  • 1 to 256 Simultaneous connections
  • Server/Client roles, configurable per connection
  • Automatically establish & tear-down connections
  • All-RTL send/receive for extremely low latency
  • Low-jitter and high sustained throughput performance
  • ARP function, server & client
  • Programmable per connection receive/congestion window
  • Monitoring function, per-session statistics
  • 64-bit AXI4 Send & Receive streams @ 156.25 MHz
  • Internal Block RAM or External DDR3 buffers
  • Configurable TX & RX buffer size: 1KB-1GB

Lower Layer IP Blocks PHY Side

Contact us for datasheet and pricing