25G LL MAC/PCS IP Core
Ultra Low- Latency 25-Gbit/s Ethernet MAC & PCS/PMA.
The 25G LL MAC/PCS combines Chevin Technology’s 25GMAC and 25GPCS IP cores to significantly increase the efficiency and rate of data transfer by providing lowest possible latency. Achieve Ultra Low-Latency and smooth integration for your FPGA project using Chevin Technology’s 25G Ethernet IP cores. The IEEE 802.3by compliant 25G LL MAC/PCS was designed here at Chevin Technology, so we offer a detailed user guide and expert support and design services to assist in the implementation of 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. A reference design is available for eco-system partner Alpha Data’s ADM-PCIE-8V3, ADM-PCE-9V3 boards. The 25G LL MAC/PCS is also compatible with Xilinx’s VCU108 board and has been tested with the Mellanox MCX4121A-ACAT NIC. Flexible licensing terms are available with Chevin Technology IP cores, to allow for the unique requirements of each customers’ project.
Contact us for a free evaluation of the super-fast packet round trip time of 119.5 ns on your Virtex® UltraScale™ FPGA.
| Chevin Technology 25G Ethernet IP Cores | ||
|---|---|---|
| PRODUCT | Full Packet Round Trip Time | LUTS |
| (RTT) | ||
| 25GMAC | 20.5ns | 2680 |
| 25GPCS/PMA | 99ns | 5250 |
| 25G LL MAC/ PCS | 119.5ns | 7930 |
| 25G UDP | – | 1348 |
| 25G TCP | – | – |
Key Features
- Designed to IEEE 802.3by specifications, 25GBASE-R
- Combined 7930 LUTs
- Ultra-Low Latency: 119.5 nanosecond packet Round Trip Time (RTT) on Xilinx Virtex® UltraScale™
- Cut-through mode operation for minimum latency
- Deficit Idle Count / Programmable IFG– Minimize IFG
- Fault Management, BER monitoring
- Statistics counters for frames and bytes sent/received, size bins, FCS errors, broadcast
Download Product Brief
CT1029-25GbE-LL-MAC/PCS Product Brief – Version 1.1
