Chevin Technology’s 10G & 25G UDP Ethernet IP is FPGA Synthesisable EndPoint with Checksum Offload for ultra low-latency connectivity.
The 10G & 25G UDP IP cores simplify FPGA integration of an ultra fast UDP/IP layer in any FPGA by handling the complete Ethernet frame assembly.
A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the “user data” payload is exchanged between the application and the UDP block. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi- port application is supported by a single UDP IP core by using the udp_port sideband embedded in the streaming interface.
Latency Figures: TX 38.4 ns, RX 38.4 ns
Round trip delay MAC -> APP -> MAC 102.4ns ( Figures include 33.6ns of inherent protocol latency)
FPGA Resource Figures: Virtex UltraScale: 2480 LUTs; Kintex Ultrascale: 2480 LUTs; Kintex-7: 3088 LUTs
- AXI4s MAC & Application Interfaces
- Reference Design on AlphaData ADM-PCIE-KU3 board
- Compose/Decompose complete UDP Datagrams
- IP frame Checksum Generator/Checker
- Jumbo frame support up to 32k
- Configurable operation port filtering
- 1-64k Ports (configurable ports & filters)
- Detailed traffic analysis statistics collection
- Integrated Streaming FIFO – 4 Block RAMs
- Integrated IP Checksum Generator/Check
- Flow Control between MAC/User logic
- Consistently low and predictable latency with zero frame jitter
Lower Layer IP blocks
CT1009-XGMAC 10Gbit/s Ethernet MAC for low-latency/high performance FPGA applications
CT1006-XGARP/ICMP 10Gbit/s Ethernet layers for complete FPGA hosted application with ARP and ICMP “ping”
CT1010-XGPCS 10Gbit/s Ethernet PCS for ultra low-latency 64b66b coding & SERDES to 10.3125Gbit line rate