XGPCS – 10Gbit/s Ethernet PCS IP for FPGAs

FPGA Synthesisable 10Gbit/s Ethernet PCS code for ultra-low latency 10Gbit/s connectivity 10GBASE-R

The CT1010-XGPCS IP block simplifies FPGA integration of an ultra fast 10Gbit/s Ethernet PCS Layer in FPGA

IEEE802.3ae-2002 specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox

Proven on Alpha-Data ADM-PCIE-KU3 board to reduce PCS latency down to 42.3ns each way between XGMII and XSBI interfaces

Key Features

  • 10Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3ae-2002 specification
  • Low latency, 109 ns Round trip time, XGMII -> Wire -> XGMII
  • 2404 LUTs
  • Integrated 64b66b codec, scrambler/descrambler and gearbox 66/32bit
  • Fault management
  • BER monitoring
  • PRBS pattern generator/checker
  • Statistics block


  • XGMII Interface to MAC directly or via XAUI
  • Encrypyted Netlist / Encrypted Source Code
  • MDIO interface Clause 49

Upper Layers IP blocks

  • CT1009-XGMAC 10Gbit MAC for low-latency/ high-performance FPGA applications
  • CT1006-XGARP/ICMP 10Gbit layers for complete FPGA hosted application with ARP and “ping”
  • CT1012-XGUDP 10Gbit UDP EndPoint for FPGA applications

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