25G PCS – 25Gbit/s Ethernet PCS

FPGA Synthesisable 25Gbit/s Ethernet PCS code for ultra-low latency 25Gbit/s connectivity 25GBASE-R

The CT1026-25GPCS IP block simplifies FPGA integration of an ultra fast 25Gbit/s Ethernet PCS Layer in FPGA

IEEE802.3by specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox

Proven on Alpha-Data ADM-PCIE-8V3 board to reduce PCS latency down to 99ns between XGMII and XSBI interfaces.

Key Features

  • 25Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3by specification
  • Low latency, 99 ns Round trip time, XGMII -> Wire -> XGMII
  • 5250 LUTs
  • Integrated 64b66b codec, scrambler/descrambler and gearbox 66/32bit
  • Fault management
  • BER monitoring
  • PRBS pattern generator/checker
  • Statistics block

Options

  • Encrypyted Netlist

Upper Layers IP blocks

  • CT1025-25GMAC 25Gbit MAC for low-latency/ high-performance FPGA applications
  • CT1006-XGARP/ICMP 25Gbit layers for complete FPGA hosted application with ARP and “ping”

 

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