25G MAC – 25Gbit/s Ethernet MAC

The 25GMAC IP core is an Ultra Low-Latency 25Gbit/s Ethernet MAC with a latency of 20.5ns in 2680 LUTs. When combined with the Ultra Low-Latency 25GPCS, the full packet round trip time ( MAC Input -> Wire -> MAC Output ) is 128ns in 7930 LUTs.

The XGMAC complies with the IEEE802.3by specification, and provides an easy path to the integration of protocols such as TCP/IP and UDP protocols in an FPGA, whilst using minimal FPGA resources. The 25GMAC simplifies the synthesis of ultra fast Duplex 25Gbit/s Ethernet for FPGAs.

We understand that efficiency is crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 390.625MHz.

Latency of the 25GMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 8 nanoseconds after arriving at 25GMII. Alternatively, the Store-and-Forward mode reduces application workload, as the 25GMAC drops all corrupt frames. The Frame Checksum verifies frame integrity; the CRC32 check result is available 8 nanoseconds after the final byte is received.

The Deficit Idle Count optimizes the Inter Frame Gap (IFG) for absolute maximum Throughput and minimum Latency by maintaining an average IFG count.

 

Chevin Technology 25G Ethernet IP Cores

PRODUCT

Full Packet Round Trip Time

(RTT) 

LUTS

25GMAC

20.5ns

2680

25GPCS/PMA

99ns

 

5250

 

25G LL MAC/ PCS

119.5ns

7930

25G UDP

1348

25G TCP

 

Key Features

  • 25Gbit Ethernet Connectivity in Xilinx FPGA
  • Designed to IEEE 802.3by specification
  • Low latency, TX 11ns, RX 8ns (Modes: cut-through/store-and-forward)
  • Integrated FCS(CRC32) checker and generator
  • Small Footprint, Virtex UltraScale 2680 LUTs / 2 Block RAMs
  • Pause packet generate/accept
  • Deficit Idle Control / Programmable IFG, less gaps, more throughput
  • Store-and-forward /Cut-Through FIFO modes for minimum workload/latency
  • Statistics counters, TX and RX traffic stats collected in size bins, frame type, FCS errors
  • Local/Remote fault handling at RS Sub-Layer
  • MAC Filter/Promiscuous Mode
  • Easy to integrate, simple host interface to registers and statistics table.

Options

  • Xilinx AXI4 streaming interface
  • VLAN 802.1Q & PFC priority flow control
  • IEEE 1588 Precision Time Protocol
  • Advanced Hash Table based Filters, MAC address, IP, TCP/UDP port
  • Encrypted Netlist

Lower Layer IP Blocks Network Side

  • Connect to SFP28 (copper Direct Attach or optical Fibre) with Chevin Technology 25GPCS (PCS-PMA,25GBASE-R)
  • Connect to back-plane

Upper Layers IP Blocks Application Side

  • Add RTL-hardened functions for ICMP and ARP to any application using XGARP/ICMP

 

 

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