10G LL MAC/PCS IP Core

Achieve optimal data transfer time on your FPGA using the 10GLLMAC/PCS,  an IP stack that combines Chevin Technology’s Ultra               Low- Latency 10-Gbit/s Ethernet XG MAC,and XG PCS/PMA IP cores.

Reference designs are available for our ecosystem partner Alpha Data’s ADM-PCIE-KU3, ADM-PCIE-8V3, ADM-PCIE-9V3 boards.                   Contact us for a free evaluation of the fast packet round trip time of 160 ns on your Virtex or Kintex® UltraScale™ FPGA.

Key Features

  • Cut-through mode operation for minimum latency
  • Deficit Idle Count / Programmable IFG– Minimize IFG
  • Designed to IEEE 802.3-2008; IEEE 802.3ae-2002 specifications, 10GBASE-R
  • Fault Management, BER monitoring
  • Small Footprint; Combined 5153 LUTs & 2 Block RAMs
  • Statistics counters for frames and bytes sent/received, size bins, FCS errors, broadcast
  • Ultra-Low Latency: 153.8 nanosecond packet Round Trip Time (RTT) in Kintex® UltraScale™

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